SCKBDIFFOPT=SCKBDIFFOPT_0, CLRAHBBUFOPT=CLRAHBBUFOPT_0, SAMEDEVICEEN=SAMEDEVICEEN_0
Module Control Register 2
| CLRAHBBUFOPT | This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. 0 (CLRAHBBUFOPT_0): AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. 1 (CLRAHBBUFOPT_1): AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. |
| CLRLEARNPHASE | The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately. |
| SAMEDEVICEEN | All external devices are same devices (both in types and size) for A1/A2/B1/B2. 0 (SAMEDEVICEEN_0): In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored. 1 (SAMEDEVICEEN_1): FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. |
| SCKBDIFFOPT | B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK). In this case, port B flash access is not available. After changing the value of this field, MCR0[SWRESET] should be set. 0 (SCKBDIFFOPT_0): B_SCLK pad is used as port B SCLK clock output. Port B flash access is available. 1 (SCKBDIFFOPT_1): B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available. |
| RESUMEWAIT | Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed. |